1. Field of the Invention
The invention relates to computer systems and more particularly to a computer system including a bus having a relatively high bandwidth and a relatively low pin count.
2. Description of the Related Art
Traditional personal computer architectures partition the computer system into the various blocks as shown in FIG. 1. The central feature of this prior art architecture is the use of the Peripheral Component Interface (PCI) bus 101 as the connection between the "north bridge" integrated circuit 103 and the "south bridge" integrated circuit 105. The north bridge functions generally as a switch connecting CPU 107, a graphics bus 109 such as the Advanced Graphics Port (AGP) bus, and the PCI bus to main memory 111. The memory controller function is also located in the north bridge.
The south bridge generally provides the interface to the input/output (I/O) portion of the system with the exception of video output as illustrated in the prior art computer architecture shown of FIG. 1. Specifically, the south bridge 105 provides a bridge between the PCI bus and legacy PC-AT (Advanced Technology) logic. The south bridge also provides a bridge to the legacy ISA bus 115, the Integrated Device Electronics (IDE) disk interface 117 and the Universal Serial Bus (USB) 119. The various busses and devices shown in FIG. 1 are conventional and are not described further herein unless necessary for an understanding of the present invention.
In the illustrated prior art architecture, the PCI bus between the north bridge and the south bridge also functions as the interconnect bus for many add-in functions. That results in a significant number of pins on the north bridge circuit 103 and the south bridge circuit 105 to account for the add-in functions. That also results in a lack of determinism in the system because any function on the PCI bus can become master of the bus and tie up the bus. Ideally, communication between the CPU and the resources in the south bridge, or between the resources in or coupled to the south bridge and system memory 111 should be deterministic in the sense of knowing what throughput is available for a particular transfer and the latency that is involved for that transfer.
It would be desirable to have a deterministic system for the major interconnect bus and in addition to reduce the pressure for additional pins on the integrated circuits making up the computer system.